As monolithic dynamic random access memory (DRAM) arrays increase in density, it becomes more likely, from a statistical standpoint, that one or more shorts will exist between a word line (generally referred to as a "row" within the array) and a digit line (generally referred to as a "column" within the array). For 4-megabit DRAMs, the probability of having one or more row-to-column shorts on a single die ranges between approximately ten and twenty percent, depending on the particular manufacturing process utilized. The principal causes of such shorts are particle contamination and process variability. Even manufacturers having the very cleanest of fabrication facilities and the most carefully controlled of manufacturing processes are not immune from these yield-reducing factors.
As a aid to understanding the complexities associated with row-to-column shorts, a brief explanation of the operation of a DRAM array will be undertaken.
A DRAM array comprises a multiplicity of capacitors, each of which is associated with a single memory cell. Each capacitor stores a single bit of data, which is accessible through an access transistor exclusive to that cell, which, along with other cell access transistors in the same array row, is turned on by activating a single word line. All capacitors within the array have a common node, which is referred to as the cell plate. The voltage of the cell plate is held to approximately V.sub.cc /2 (V.sub.cc being the voltage supplied to the chip). A "1" is stored in the capacitor of a memory cell by charging the capacitor's uncommon node (the storage node plate) to V.sub.cc through the access transistor. Likewise, a "0" is stored by discharging the uncommon node to V.sub.ss (generally ground potential) through the access transistor. The charge on a cell capacitor is read by first equilibrating the cell plate and all digit lines to V.sub.cc /2. After the equilibration voltage is disconnected from the digit lines, the cell access transistor is turned on, dumping the charge stored in the cell's capacitor to one of the digit lines. If the storage node plate had been charged to V.sub.cc, the voltage on that digit line will be increased slightly. Likewise, if the storage node plate had been grounded to V.sub.ss, the voltage on that digit line will be decreased slightly. An adjacent digit line, to which no charge has been dumped during this read cycle, is used as a reference. The voltage differential between the two digit lines will be within a range of approximately 200 to 200 mV. This differential voltage is then amplified by cross-coupled N-channel and P-channel transistors (sense amplifiers), which respectively pull the digit line having the slightly lower voltage to V.sub.ss and the digit line having the slightly higher voltage to V.sub.cc. Once this has occurred, the voltages on the digit lines are passed out of the array to a column decoder and read by an output buffer. FIG. 1 graphically depicts the voltages of two digit line pairs (DLP1 and DLP2) as a function of RAS (row address strobe) and word line voltages over the identical time period. The voltage levels on first digit line pair DLP1 are representative of a read operation where a "1" has been stored in the cell being read; those on digit line pair DLP2 are representative of a read operation where a "0" has been stored in the cell being read. Such voltage-time relationships are commonly observed in CMOS DRAM arrays having a folded digit line architecture. If a new value is to be stored in a DRAM cell after the read operation, the polarity of the digit lines may be reversed by write voltages from peripheral drivers passed through the column decoder. Thus, with the cell access transistor turned on, a write voltage on the associated digit line is applied to the cell's storage node plate. When the cell access transistor is turned off (this even corresponds to RAS going high), the digit line voltage (whether V.sub.cc or V.sub.ss) remains on the storage node plate. Since this charge on the storage node capacitor plate is subject to leakage, the cell must be refreshed periodically by performing a "dummy" read operation.
Typical DRAM specifications require that digit lines, once equilibrated to V.sub.cc /2, maintain that voltage for up to 16 milliseconds for a standard part, and up to 128 milliseconds for a lower power part. During this time, if the digit lines are not tied to a small bias generator, which produces a voltage of approximately V.sub.cc /2, they will leak to a lower level (if sufficient time were allowed, they would leak to V.sub.ss), and the following read operation may consequently fail.
FIG. 2 shows a typical method used to both equilibrate the digit lines and maintain the digit lines at a voltage approximately equal to V.sub.cc /2. Equilibrate signal EQ will go high after the word line WL is turned off, and will connect each of transistors Q1.sub.n and Q2.sub.n to both a digit line and to a bias voltage generator output DVC. A simply bias voltage generator 21 is shown. A bias voltage generator on the DRAM chip itself provides a regulated voltage approximately equal to V.sub.cc /2 over a known current range. At this time, all word lines are held at V.sub.ss. If a row-to-column short 22 exists within the array, the word line WL, which is being held at V.sub.ss, would be connected through transistors Q1.sub.1 and Q2.sub.1, to the bias generator output. If the bias generator output is sufficiently large, then the bias generator output voltage will remain at or near V.sub.cc /2. However, typical DRAM data sheet specifications require the power supply current to be below 1 milliampere while RAS is high. Thus the row-to-column short could cause the part to fail its standby current specification and, thus, be rendered unacceptable. If the bias generator has a limited current output capability, then the row-to-column short would cause all digit lines in the part to fall towards V.sub.ss. FIG. 3 provides a graphic representation of the fall-off in voltage that is characteristic of a badly shorted array after RAS goes high and the word line is brought low. At some point, there will be insufficient voltage on the digit lines for the N-sense amplifiers associated therewith to latch the data thereon, resulting in an invalid read operation and possible loss of data. Referring once again to FIG. 2, if the cell plate CP is common to the bias voltage generator bus 23 (such an architecture would be represented by switch SW1 closed and switch SW2 opened), instead of having its own V.sub.cc /2 bias voltage generator 24 (such an architecture would be represented by switch SW1 opened and switch SW2 closed), and if the row-to-column shorts within the array cause the chip to draw more current then the rated output of bias voltage generator, the cell plate CP will be biased at a voltage less than V.sub.cc /2. The voltage on the cell plate may even fall to V.sub.ss. such a precipitous drop in cell plate bias voltage may well result in the overstressing of the cell dielectric layer, which is designed to reliably handle a voltage less than V.sub.cc /2. Thus, given the scenario where the bias voltage drops to V.sub.ss after a long RAS high time, the voltage across the capacitor dielectric would be twice the design voltage. Many of the cells within the array may become damaged during subsequent read operations, with their capacitors permanently shorted.
Still referring to FIG. 2, another problem associated with row-to-column shorts is that of what will be herein termed the "sneak" path from the bias voltage generator bus 23 to ground. During the time that RAS is high it is customary to switch the common node 25 of the P-type sense amp (SA1 in this schematic) from a V.sub.cc voltage level to the bias voltage generator bus 23, which has a voltage level of V.sub.cc /2. This is done to prevent current flow through the transistors of each P-type sense amplifier, from either of the associated digit lines, which would tend to pull the common node low and potentially create a voltage imbalance on the digit lines during equilibration. If a row-to-column short exists on at least one of the associated digit lines, and the common node is being held at V.sub.cc /2 during equilibration, current will flow from the common node 25, through one of the transistors of P-type sense amp SA1, to the shorted digit line, and to the associated digit line through equilibration transistors Q1.sub.1 and Q2.sub.1. Thus, with common node 25 connected to bias voltage generator bus 23, a row-to-column short will place an unacceptable load on bias voltage generator 23 through this additional path, with the same deleterious effects as described above.
By creating spare rows and spare columns within a DRAM array in combination with address redirection circuitry, it is possible to substitute functional spare rows and columns for those that are shorted--at least to the extent that shorted rows and columns do not exceed the number of spare rows and columns. It is important to realize that the shorted columns are rows are not disconnected from the array circuitry. The are simply no longer addressed by the array's address decode circuitry. Disconnection of shorted rows and columns from the array circuitry is impractical--if not impossible--with presently available technology, due to the small inter-word line and inter-digit line pitch used to fabricate DRAM arrays. Schemes for implementing row and column redundancy in DRAM arrays are well known in the art and will not be discussed in further detail in this document.
In light of the foregoing discussion of DRAM operation, it is clear that repair of row-to-column shorts through redirected addressing will not eliminate the presence of shorts within the array, nor will it eliminate the potential for bias voltage pull down, with the attendant problems of excessive standby current, read/write operations resulting in invalid data, and possible damage to cell capacitors within the array.
Hitachi Corporation of Japan has addressed the problem of row-to-column shorts in its 256 megabit DRAM. The chip's memory array is divided into four quadrants, each of which has 64 normal sur-arrays and 2 spare sub-arrays. Whenever a sub-array has a row-to-column short, it is disconnected from the active circuitry and replaced by a spare sub-array. According to Hitachi, the chip area penalty associated with this sub-array replace scheme is 3.5%. Although such a penalty may not seem to be significant, it should be noted that the profit margin for the current generation of DRAMs is probably less than 3.5% for most manufacturers.
What is needed is a solution to the row-to-column short problem that imposes little or no chip area penalty.